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| yosys-0.61-1.20260115git967b47d.fc42 | Yosys Open SYnthesis Suite, including Verilog synthesizer | linux/aarch64![]() |
| yosys-devel-0.61-1.20260115git967b47d.fc42 | Development files to build Yosys synthesizer plugins | linux/aarch64![]() |
| yosys-doc-0.61-1.20260115git967b47d.fc42 | Documentation for Yosys synthesizer | linux/aarch64![]() |
| yosys-share-0.61-1.20260115git967b47d.fc42 | Architecture-independent Yosys files | linux/noarch![]() |
| yosyshq-abc-0.61-2.20260115git799ba63.fc42 | Sequential logic synthesis and formal verification | linux/aarch64![]() |
| yosyshq-abc-devel-0.61-2.20260115git799ba63.fc42 | Headers and libraries for developing with ABC | linux/aarch64![]() |
| yosyshq-abc-libs-0.61-2.20260115git799ba63.fc42 | Library for sequential synthesis and verification | linux/aarch64![]() |
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Fabrice Bellet, Sat Jan 17 23:35:39 2026