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| yosys-0.60-1.20251205git0e31e38.fc42 | Yosys Open SYnthesis Suite, including Verilog synthesizer | linux/aarch64 |
| yosys-devel-0.60-1.20251205git0e31e38.fc42 | Development files to build Yosys synthesizer plugins | linux/aarch64 |
| yosys-doc-0.60-1.20251205git0e31e38.fc42 | Documentation for Yosys synthesizer | linux/aarch64 |
| yosys-share-0.60-1.20251205git0e31e38.fc42 | Architecture-independent Yosys files | linux/noarch |
| yosyshq-abc-0.60-1.20251205git49efc5b.fc42 | Sequential logic synthesis and formal verification | linux/aarch64 |
| yosyshq-abc-devel-0.60-1.20251205git49efc5b.fc42 | Headers and libraries for developing with ABC | linux/aarch64 |
| yosyshq-abc-libs-0.60-1.20251205git49efc5b.fc42 | Library for sequential synthesis and verification | linux/aarch64 |
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Fabrice Bellet, Mon Dec 15 23:51:49 2025