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| Name: CoreFreq | Distribution: openSUSE Tumbleweed |
| Version: 1.97.1 | Vendor: openSUSE |
| Release: 1.3 | Build date: Fri Apr 5 22:44:18 2024 |
| Group: Unspecified | Build host: reproducible |
| Size: 1440381 | Source RPM: CoreFreq-1.97.1-1.3.src.rpm |
| Packager: https://bugs.opensuse.org | |
| Url: https://github.com/cyring/CoreFreq | |
| Summary: CPU monitoring software for 64-bit processors | |
A CPU monitoring software with BIOS-like functionalities for 64-bit processors like Intel Atom, Core2, Nehalem, SandyBridge and superiors, and AMD Families 0Fh–17h (Zen), 18h (Hygon Dhyana).
GPL-2.0-or-later
* Fri Apr 05 2024 Michael Pujos <pujos.michael@gmail.com>
- added preamble file for %kernel_module_package macro
- update to 1.97.1
* added aarch64 support
* upstream did not provide a summary changelog. Full list of commits:
https://github.com/cyring/CoreFreq/compare/1.96.5...1.97.1
* Sat Jul 01 2023 Michael Pujos <pujos.michael@gmail.com>
- update to 1.96.5
* [AMD]
Adding the "AMD Ryzen 5 5600X3D"
Introducing the Zen4c Bergamo architecture
Specs fixing of Embedded V-series and 3000 Series Processors
Adding MENDOCINO, RAPHAEL Pro, PHOENIX Pro among others
* Thu Jun 15 2023 Michael Pujos <pujos.michael@gmail.com>
- update to 1.96.4
* [AMD]
- Display CPUID state of new and legacy features:
Fused Multiply Add [FMA4]
Extended Operation Support [XOP]
Translation Cache Extension [TCE]
Trailing Bit Manipulation [TBM]
OS Visible Work-around [OSVW]
LOCK prefix to read CR8 [AltMov]
* [Intel]
- Advanced Matrix Extensions [AMX]
- Bits and Features of Sierra Forest and Grand Ridge
- Attempt to decode the Meteor Lake Memory Controller
- update to 1.96.3
* [AMD]
- [Zeppelin] Probe more than one UMC controllers on Ryzen Threadripper 1900X
- [Zen4] Dump SMBE and BMEC sub-leaves of CPUID 0x80000020
* Sun Jun 04 2023 Michael Pujos <pujos.michael@gmail.com>
- update to 1.96.2
* [Driver]
- Allows compilation to keep going without CONFIG_ACPI_CPPC_LIB
* [Client]
- Adding two command line arguments:
- Op Show Package C-States
- OW Toggle Energy units
* [AMD]
- Specification of some Configuration MSRs
* Sun May 14 2023 Michael Pujos <pujos.michael@gmail.com>
- update to 1.96.1
* [Driver]
- Postpone Clock Source registration during startup until the Base Clock is computed.
- Change class_create() according to Linux Kernel 6.4
- Clear interrupt flag (cli) after Halt in the Idle method
* [AMD]
- [PHOENIX] Adding Ryzen 7940H, 7840H, 7640H
- [VERMEER] Adding Ryzen PRO and Embedded processors
- Ryzen Z1 CPUID' brand fix
- Adding EPYC Embedded 9004 Series as Genoa
- Adding EPYC Embedded 7003 Series as Milan
- Adding EPYC Embedded 7002 Series as Rome
- Adding EPYC Embedded 7001 Series as Naples
* Wed May 03 2023 Michael Pujos <pujos.michael@gmail.com>
- removed leap_compile_fix.patch no needed anymore
- update to 1.96.0
* [AMD]
[RPL/X3D] Disabling the turbo boosted P-states change
[PHOENIX] Adding Z1, U and HS PRO series.
[Genoa] DAC address at UMC BAR + 0x40
[Zen4] Adding the PCI entries of Genoa
[Zen2] Adding remaining PCI entries
[Zen] Query DAC & CFG with the right UMC base address register
[Zen4] Dump the CPUID Extended CPU Topology leaves.
[Zen][Embedded][Banded Kestrel] R1000 Processor Family
[Zen][Embedded] "Great Horned Owl", "River Hawk", "Grey Hawk"
Complete the "Raven Ridge" and "Picasso" lists
[EPYC] Moved "Snowy Owl" Embedded processors to CPUID 8F_01
[Zen4] introducing Phoenix and Dragon Range
[RMB] adding the Ryzen Embedded V3000 processors
[VMR] adding the "AMD Ryzen 9 PRO 5945"
* [Intel]
Adding Granite Rapids, Sierra Forest, Grand Ridge entries
Adding "Lunar Lake" and "Arrow Lake" entries.
* [UI]
Optimized decimal to digits converter
Allow task tracker to select up to pid_max
Can trace the frozen states of Linux tasks.
Only print HWP frequencies within bounds.
Fix ruler's aggregation.
* [CR]
Check CPUID[HV_PARTITION_PRIVILEGE_MASK] for HV_X64_MSR_VP_RUNTIME
Uninitialized variable fix.
[CPPC] Build EPP with KERNEL_VERSION(6) rather than CONFIG_CACHY
[KERNEL] Linux 6.3: Employ modifier calls with the vma->vm_flags
* Thu Feb 23 2023 Michael Pujos <pujos.michael@gmail.com>
- added leap_compile_fix.patch to fix compilation on Leap
* Wed Feb 22 2023 Michael Pujos <pujos.michael@gmail.com>
- update to 1.95.4
* [Intel] [from 11th to 14th gen]
Convert the DRAM Speed to MT/s unit
Compute the Bus Rate based on the BIOS MC PLL
- update to 1.95.3
* [Intel] [Airmont]
Improved the IMC geometry
Introducing the Spreadtrum architecture
Fixed the Bus and DRAM frequency rates
* [Intel] [from 11th to 13th gen] Attempt to probe the interleaved controllers
* [Intel] [Alder Lake/H] Attempt to decode the TCO Watchdog
* Thu Feb 09 2023 Dirk Müller <dmueller@suse.com>
- update to 1.95.2:
* Fixed the aggregation of the minimum ratio
Intel:
* [Airmont][Silvermont] Attempt to decode `tCKE` from DRMC
register
* [Airmont] Improve `tWTPr`, `B2B`, `tWWDR` timings
* [Airmont] Provide a new IMC decoder
* Add the Emerald Rapids architecture entry
* [DDR5][DDR4] Add the `RCDw` IMC timing
* [Raptor Lake ] De-activate the MSR Uncore counter
AMD:
* "Zen3/Barcelo-R" and "Zen3+ Rembrandt-R" codenames
* [Zen] Thermal highest limit reset fix
Misc:
* Code review and Registers documentation:
AMD HWCR, Intel HDC and DRP
* Mon Jan 23 2023 Dirk Müller <dmueller@suse.com>
- update to 1.95.1:
* [Intel] RPL: voltage of Pcore, Ecore, System Agent
* [Intel] RPL and ADL Chipset device IDs
* [Intel] Decode the RPL IMC and improve DDR5 support
* [Build] Raise `MAX_FREQ_HZ` up to 7125000000 Hertz
* [Intel] Mobile {Coffee Lake, Kaby Lake} codenames
* [Intel] Braswell codename detection
* [AMD] SYSCFG Register
* [AMD] EPYC 9654
* [AMD] Transparent SME
* [AMD] DRAM Data Scrambling
* [AMD] Adding "Barcelo R" and "Rembrandt R"
* Fri Jan 06 2023 Dirk Müller <dmueller@suse.com>
- update to 1.94.3:
* [AMD][RMB] If UMC is quad channels then unpopulate odd channels
* [AMD][RPL] Provide Service Processor Vcore as workaround
* [UI] Auto size and lay performance capabilities window
* [UI] Adding comments to the EEO and R2H technologies
* [AMD][Raphael] 7950X3D, 7900X3D. support
* Tue Jan 03 2023 Dirk Müller <dmueller@suse.com>
- update to 1.94.1:
* [Intel] Gemini Lake
* [AMD] Ryzen 5 6600 H SoC, UMC channels
* [AMD] Rembrandt: maximum of two UMC channels
* [AMD] Raphael: Decodes DIMM geometry from AddrCfg
* [AMD] Zen: Aggregation refactored
* [AMD] Improved DDR5 clock decoding
* Optimized Idle Loop
* Tue Dec 13 2022 Michael Pujos <pujos.michael@gmail.com>
- removed modprobe_corefreqd.service.patch and harden_corefreqd.service.patch
now included in new corefreqd.service file replacing stock one
- update to 1.93.1
* [PRJ] CoreFreq version 1.93.1
* [ACPI/CPPC/EPP] Preview of AMD/Zen Energy Preference (CONFIG_CACHY)
* [UI] Changed the HWP or CPPC ratio bounds.
* [FIX] Putting `corefreqd` in the root cgroup (issue #379) Thanks to gel-crabs
* [DOC] Parameters to blacklist the amd_pstate since kernel 6.0.11
* [AMD][Zen4] Apply a voltage formula based on Rembrandt's. (#378)
* [AMD][Zen4/Raphael] Attempting temperature per CCD from TCTL+0x308
* [AMD][Zen4] Changed Timer loop
* [CR] CLI code review and UI optimizations
* [UI] Auto refresh the Topology items when off/online
* [CR] Conditionally build with additional PMC Counters
* [Intel] Adding Z8000 System Memory Controller Registers
* [CR] Transformed global variable in cells padding
* [UI] Windows re-scaling fix
* [UI] Apply color theming to the CPPC capabilities list.
* [AMD][Raphael] Adding device DIDs to probe UMC and IOMMU
* [CPPC/FMW] Computes value bounds while Enabling/Disabling firmware
* [CR] CPPC lib errors are now raised to Debug level
* [AMD][Zen4] Increased the UMC size to 12 channels.
* [CPPC] Handles the OffLine CPU case.
* [CLI] Refactoring HWP/CPPC to print all capabilities per CPU
* [ACPI] Computes the CPPC Bounds
* [Intel] Linear Address Masking (LAM)
* [CLI] EFER: Left aligned labels
* [AMD] Reports UAIE and AIBRSE bits from EFER system register
* [CLI] Changed mitigation mechanisms incapability labels
* [AMD][Zen2] Mitigation Mechanism BTC-NOBR * ACPI/OSPM documentation
* [CR] Code review on bit masks
* [CPPC][ACPI] Kernel may decode the Guaranteed Performance Register
* [UI] Optimize the cycles to clear the time bar.
* [CR] Code review for extra compiler warnings
* [UI] Time of the day displayed in the right side of menu
* [UI] Display the current date and time in menu bar
* [Kernel] Introducing support of `CONFIG_SCHED_BORE`
* [CLI] Fixing ambiguous CPPC report: hardware vs firmware
* [CLI] Surrounds _CPC feature with square brackets
* [CPPC] Provides the ACPI _CPC object state.
* [UI] Colors the task being tracked in the tracking list
* [UI] Display the current time in the menu bar
* [CLI] Reserve the programmable TDP section to Intel processors.
* [AMD/Zen3+] Improving the DIMM geometry of Rembrandt UMC
* Mon Dec 05 2022 Dirk Müller <dmueller@suse.com>
- update to 1.92.4:
* [Intel/Skylake-X] Permits MSR_RING_PERF_LIMIT_REASONS
* Fri Nov 04 2022 Jan Engelhardt <jengelh@inai.de>
- Repair deficient description grammar.
* Fri Nov 04 2022 Michael Pujos <pujos.michael@gmail.com>
- update to version 1.92.3
- Export CPUID bits Intel Sierra Forest, Grand Ridge, Granite Rapids
and completes AMD64 Fn0000_0007_ECX_x0
- [Features] WBNOINVD and CLZERO instructions
- Adding various Mitigation Mechanism aggregations:
IPRED_DIS_U, IPRED_DIS_S, RRSBA_DIS_U, RRSBA_DIS_S, BHI_DIS_S, MCDT_NO
- RDPID and UMIP capability fixed.
- [AMD] Perf. Mon. version based on CPUID_0x80000022.EAX.PerfMonV2
- [AMD][Zen3+][Rembrandt] Trigger UMC and IOMMU decoders
- [AMD][Ryzen 5 6600H] Found voltage VID @ SMU 0x6f010 and 0x6f014
- Introducing AMD Security Feature capabilities:
SKINIT, SEV, GMET, SEV-ES, SEV-SNP
- [AMD64] Non-architectural MSR: SPECULATIVE STORE BYPASS DISABLE
- [Intel][2nd & 3rd gen] Misc IMC optimizations
- [AMD][Rembrandt] Provides Vcore from a new formula.
- Dumping CPUID leaves from AMD64 Architecture Programmer’s Manual
- [Intel][HSW & BDW] Compute the DIMM banks
- [UI] Re-assigned keys to move or resize windows.
- [AMD][Zen] Uncore frequency: Improving the Memory Clock divisor
- [Intel][HSW & BDW][SKL] Make use of same function DimmWidthToRows
- [AMD][Zen3+][Rembrandt] Provides the thermal sensor.
- [AMD/Zen2 & Zen3] Removed the HSMP capability.
- [Intel][CML][RKL][TGL] Compute the DIMM Rows from CH_WIDTH
- [AMD/EPYC] Adding the CPUID of Zen4 Genoa architecture
- [AMD/Zen2] Introducing Mendocino architecture
- Changed MeteorLake/N to CPUID 06_B5
- [Intel] Computes BIOS DRAM frequency based on PLL_REF100
- [Intel][SNB/IVB/HSW/BDW] Improved BIOS DRAM frequency
- [Intel][SNB/IVB] DRAM frequency based on RAM_Select and FSB_Select
- [Intel][IVB] IMC specifications and optimizations.
- [Intel][SNB,IVB] Computes the DIMM A from DAS bit in MAD register
- [Intel][SNB,IVB,HSW,BDW] Rolling back changes to the DIMM topology
- [Intel][BDW][HSW] Query the IMC Power Down Mode
- [Intel][IVB][SNB] Attempt to decode the IMC third timings
- [AMD][Ryzen] Added AMD Ryzen 7 PRO 6860Z
- [AMD][F17h-F19h] Can toggle ON and OFF the Instruction Cache Unit
- [AMD] Checking the Ryzen "OEM Only" processors
- [Intel] Specification of 12th Gen. MSR registers capability
- [Intel] Adding Raptor Lake-S with CPUID 06_BF
- [AMD] Introducing Zen 4 / Raphael architecture
- [Intel][SNB,IVB,HSW] Attempt to assign the Rank per DIMM slot
- [Intel][SNB,IVB,HSW] Attempt to fix the DIMM(s) topology layout
- ClockSource: TSC udelay() asm implementation builtin as a default
- [Intel][Alder Lake] Adding IMC entry for i5-12500 processor
- [Intel][Alder Lake] Added default case if Processor has only Pcores
- [Intel][Atom/Bonnell][IMC] Attempt to compute the DIMM geometry
- [UI][Custom view] Show the Uncore unit in watt or joule
- [UI] Display HWP or CPPC in footer for capable processors.
- [CLI] Added HWP Capabilities and HWP Request to the JSON export
- [CLI] Don't allow the HWP dialog box if feature is not available.
- [CPPC][Firmware] allows (de)activation of the feature.
- [CLI] Added CPU ratios to JSON export
- [CPPC] Improved scaling
- [CPPC] Build fixed down to Kernel version 3
- [Kernel/ACPI] Attempt to write CPPC registers
* Mon Aug 22 2022 Michael Pujos <pujos.michael@gmail.com>
- Update to version 1.91.6
- [AMD/Zen][UMC] Fixed the Mem Clock and ECC regressions
- Designate the Package identifier in Power consumed readings
- [Intel/ADL/IMC] Guessing activated channel from the populated DIMM
- [AMD][UMC, IOMMU] Adding missing DID of family 19h devices
- [AMD_DataFabric_Cezanne] Removed the Experimental mode
- Intel/ADL/IMC: Fixing the Memory Channels count
- [AMD/Zen] Improved UMC mapping. Threadripper 3960X issue
- Avoid some NULL pointer strings during SMBIOS decoding
* Wed Jun 22 2022 Michael Pujos <pujos.michael@gmail.com>
- Update to version 1.91.3
* No changelog was made available by upstream
* Mon Mar 07 2022 Michael Pujos <pujos.michael@gmail.com>
- removed non-working leap15_2.patch and leap15_3.patch:
Leap 15.4 is the minimum supported version
- Update to version 1.90.1
* support for Alder Lake architecture:
in particular, specialized monitoring for Pcore and Ecore
* more precise DDR5 and DDR4 timings from SKL to ADL:
introduction of "Gear mode"
* improvement using Power Limiters:
zero W on PL1 & PL2; DRAM clampig marked experimental
* characteristics for Zen architecture:
CPPC; C1E; MEM CLOCK in raw frequency
* C-state Core for Ice Lake/X
* various characteristics of C-state package for AMD/Zen and Intel (Lake)
* various changes in UI
* non-regression tests for kernels 5.16.12 and 5.17.rc6
* Sat Feb 12 2022 Michael Pujos <pujos.michael@gmail.com>
- Update to version 1.89.3
* No changelog was made available by upstream
* Sun Oct 10 2021 Michael Pujos <pujos.michael@gmail.com>
- Update to version 1.87.4
- fixed service hardening preventing daemon to start (boo#1191509)
- added modprobe_corefreqd.service.patch to load/unload kernel
module on service start/stop. Do not load module on boot anymore
- fixed leap15_3.patch including unnessary junk
* Tue Sep 07 2021 Michael Pujos <pujos.michael@gmail.com>
- Update to version 1.87.1
* Tue Jul 27 2021 Johannes Segitz <jsegitz@suse.com>
- Added hardening to systemd service(s). Added harden_corefreqd.service.patch
* Sat Jul 03 2021 Ferdinand Thiessen <rpm@fthiessen.de>
- Update to version 1.86.7
* AMD/Zen: Improve SMT counters built on VPMC
* AMD/Matisse & Zen3: Can alter the Power Limit with a PL1 offset
* AMD/SMU: Provides the firmware and interface version
* AMD HSMP: Support Host System Management Port.
* AMD IOMMU Base Address Register fix.
* Intel/Nehalem: Altering the TDC limit
* Intel: Integration of the 11th Generation
* UI: Stream buffer memory overlap fix.
* UI: Support color theming and introducing the Strawberry theme.
* Driver: New 'CPU_Count' argument
* New parameter "WDT_Enable" to toggle the Watchdog Timer.
* Page fault fix when unregistering idle device percpu structure
* Avoid a kernel zero division in clocksource_register_khz()
* Various bug fixes and minor improvements
* Sat May 08 2021 Michael Pujos <pujos.michael@gmail.com>
- updated to v1.84.5
Fixes compilation on kernel 5.12
See commits on https://github.com/cyring/CoreFreq/commits/master
for full change list
* Thu Apr 15 2021 Michael Pujos <pujos.michael@gmail.com>
- updated to v1.84.1
See commits on https://github.com/cyring/CoreFreq/commits/master
for changes list
- added patch leap15_3.patch: fix failure to build on Leap 15.3
/usr/bin/corefreq-cli /usr/bin/corefreqd /usr/lib/systemd/system/corefreqd.service /usr/sbin/rccorefreqd /usr/share/doc/packages/CoreFreq /usr/share/doc/packages/CoreFreq/README.md /usr/share/licenses/CoreFreq /usr/share/licenses/CoreFreq/LICENSE
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