Subject: ANNOUNCE: Verilog
From: [email-masked] (Wilson P. Snyder II)
Date: 17 Jun 1999 15:18:17 GMT
Newsgroups: comp.lang.perl.announce,comp.lang.perl.modules

Verilog is a hardware description language adopted by many EE CAD vendors,
and a IEEE standard.  These modules provide some simple parsing and
language features and will expand to more advanced features.

Verilog::* is in CPAN, but they have not been indexed under the Verilog top
level name.  If the moderators could fix that, I would appreciate it.

9) Interfaces to or Emulations of Other Programming Languages

Name           DSLI  Description                                  Info
-----------    ----  -------------------------------------------- -----
Verilog::
::Pli          Rdch  Access to simulator functions                WSNYDER
::Language     Rdpf  Language support, number parsing, etc        WSNYDER
::Parser       RdpO  Language parsing                             WSNYDER
::SigParser    RdpO  Signal and module extraction                 WSNYDER

-Wilson Snyder, [email-masked]