yosys-share-0.9-3.fc32 RPM for noarch

From Fedora 32 updates for aarch64 / Packages / y

Architecture-independent Yosys files.

Provides

• yosys-share

Requires

• rpmlib(CompressedFileNames) <= 3.0.4-1
• rpmlib(FileDigests) <= 4.6.0-1
• rpmlib(PayloadFilesHavePrefix) <= 4.0-1
• rpmlib(PayloadIsZstd) <= 5.4.18-1

License

ISC and MIT

Changelog

* Sun Apr 19 2020 Marcus A. Romer <aimylios@gmx.de> - 0.9-3
  - Update man pages from Debian
  - Add license text
* Fri Jan 31 2020 Fedora Release Engineering <releng@fedoraproject.org> - 0.9-2
  - Rebuilt for https://fedoraproject.org/wiki/Fedora_32_Mass_Rebuild
* Mon Aug 26 2019 Gabriel Somlo <gsomlo@gmail.com> - 0.9-1
  - Update to latest release
  - Spec file cleanup
* Sat Jul 27 2019 Fedora Release Engineering <releng@fedoraproject.org> - 0.8-5
  - Rebuilt for https://fedoraproject.org/wiki/Fedora_31_Mass_Rebuild
* Sun Feb 17 2019 Igor Gnatenko <ignatenkobrain@fedoraproject.org> - 0.8-4
  - Rebuild for readline 8.0
* Sun Feb 03 2019 Fedora Release Engineering <releng@fedoraproject.org> - 0.8-3
  - Rebuilt for https://fedoraproject.org/wiki/Fedora_30_Mass_Rebuild
* Sun Oct 28 2018 Jon Burgess <jburgess777@gmail.com> - 0.8-2
  - Add buildreq for g++
* Sat Oct 27 2018 Jon Burgess <jburgess777@gmail.com> - 0.8-1
  - Updated to latest upstream release
  - Make sure package built with Fedora compile flags
  - Fix assert while running tests
  - Fixes FTBFS #1606769
* Sat Jul 14 2018 Fedora Release Engineering <releng@fedoraproject.org> - 0.7-10
  - Rebuilt for https://fedoraproject.org/wiki/Fedora_29_Mass_Rebuild

Files

/usr/share/yosys
/usr/share/yosys/achronix
/usr/share/yosys/achronix/speedster22i
/usr/share/yosys/achronix/speedster22i/cells_map.v
/usr/share/yosys/achronix/speedster22i/cells_sim.v
/usr/share/yosys/adff2dff.v
/usr/share/yosys/anlogic
/usr/share/yosys/anlogic/arith_map.v
/usr/share/yosys/anlogic/cells_map.v
/usr/share/yosys/anlogic/cells_sim.v
/usr/share/yosys/anlogic/dram_init_16x4.vh
/usr/share/yosys/anlogic/drams.txt
/usr/share/yosys/anlogic/drams_map.v
/usr/share/yosys/anlogic/eagle_bb.v
/usr/share/yosys/cells.lib
/usr/share/yosys/cmp2lut.v
/usr/share/yosys/coolrunner2
/usr/share/yosys/coolrunner2/cells_latch.v
/usr/share/yosys/coolrunner2/cells_sim.v
/usr/share/yosys/coolrunner2/tff_extract.v
/usr/share/yosys/coolrunner2/xc2_dff.lib
/usr/share/yosys/dff2ff.v
/usr/share/yosys/ecp5
/usr/share/yosys/ecp5/arith_map.v
/usr/share/yosys/ecp5/bram.txt
/usr/share/yosys/ecp5/bram_conn_1.vh
/usr/share/yosys/ecp5/bram_conn_18.vh
/usr/share/yosys/ecp5/bram_conn_2.vh
/usr/share/yosys/ecp5/bram_conn_4.vh
/usr/share/yosys/ecp5/bram_conn_9.vh
/usr/share/yosys/ecp5/bram_init_1_2_4.vh
/usr/share/yosys/ecp5/bram_init_9_18_36.vh
/usr/share/yosys/ecp5/brams_map.v
/usr/share/yosys/ecp5/cells_bb.v
/usr/share/yosys/ecp5/cells_map.v
/usr/share/yosys/ecp5/cells_sim.v
/usr/share/yosys/ecp5/dram.txt
/usr/share/yosys/ecp5/drams_map.v
/usr/share/yosys/ecp5/latches_map.v
/usr/share/yosys/gate2lut.v
/usr/share/yosys/gowin
/usr/share/yosys/gowin/arith_map.v
/usr/share/yosys/gowin/bram.txt
/usr/share/yosys/gowin/brams_init3.vh
/usr/share/yosys/gowin/brams_map.v
/usr/share/yosys/gowin/cells_map.v
/usr/share/yosys/gowin/cells_sim.v
/usr/share/yosys/gowin/dram.txt
/usr/share/yosys/gowin/drams_map.v
/usr/share/yosys/greenpak4
/usr/share/yosys/greenpak4/cells_blackbox.v
/usr/share/yosys/greenpak4/cells_latch.v
/usr/share/yosys/greenpak4/cells_map.v
/usr/share/yosys/greenpak4/cells_sim.v
/usr/share/yosys/greenpak4/cells_sim_ams.v
/usr/share/yosys/greenpak4/cells_sim_digital.v
/usr/share/yosys/greenpak4/cells_sim_wip.v
/usr/share/yosys/greenpak4/gp_dff.lib
/usr/share/yosys/ice40
/usr/share/yosys/ice40/arith_map.v
/usr/share/yosys/ice40/brams.txt
/usr/share/yosys/ice40/brams_init1.vh
/usr/share/yosys/ice40/brams_init2.vh
/usr/share/yosys/ice40/brams_init3.vh
/usr/share/yosys/ice40/brams_map.v
/usr/share/yosys/ice40/cells_map.v
/usr/share/yosys/ice40/cells_sim.v
/usr/share/yosys/ice40/latches_map.v
/usr/share/yosys/intel
/usr/share/yosys/intel/a10gx
/usr/share/yosys/intel/a10gx/cells_map.v
/usr/share/yosys/intel/a10gx/cells_sim.v
/usr/share/yosys/intel/common
/usr/share/yosys/intel/common/altpll_bb.v
/usr/share/yosys/intel/common/brams.txt
/usr/share/yosys/intel/common/brams_map.v
/usr/share/yosys/intel/common/m9k_bb.v
/usr/share/yosys/intel/cyclone10
/usr/share/yosys/intel/cyclone10/cells_map.v
/usr/share/yosys/intel/cyclone10/cells_sim.v
/usr/share/yosys/intel/cycloneiv
/usr/share/yosys/intel/cycloneiv/cells_map.v
/usr/share/yosys/intel/cycloneiv/cells_sim.v
/usr/share/yosys/intel/cycloneive
/usr/share/yosys/intel/cycloneive/cells_map.v
/usr/share/yosys/intel/cycloneive/cells_sim.v
/usr/share/yosys/intel/cyclonev
/usr/share/yosys/intel/cyclonev/cells_map.v
/usr/share/yosys/intel/cyclonev/cells_sim.v
/usr/share/yosys/intel/max10
/usr/share/yosys/intel/max10/cells_map.v
/usr/share/yosys/intel/max10/cells_sim.v
/usr/share/yosys/pmux2mux.v
/usr/share/yosys/python3
/usr/share/yosys/python3/smtio.py
/usr/share/yosys/sf2
/usr/share/yosys/sf2/arith_map.v
/usr/share/yosys/sf2/cells_map.v
/usr/share/yosys/sf2/cells_sim.v
/usr/share/yosys/simcells.v
/usr/share/yosys/simlib.v
/usr/share/yosys/techmap.v
/usr/share/yosys/xilinx
/usr/share/yosys/xilinx/arith_map.v
/usr/share/yosys/xilinx/brams.txt
/usr/share/yosys/xilinx/brams_bb.v
/usr/share/yosys/xilinx/brams_init_16.vh
/usr/share/yosys/xilinx/brams_init_18.vh
/usr/share/yosys/xilinx/brams_init_32.vh
/usr/share/yosys/xilinx/brams_init_36.vh
/usr/share/yosys/xilinx/brams_map.v
/usr/share/yosys/xilinx/cells_map.v
/usr/share/yosys/xilinx/cells_sim.v
/usr/share/yosys/xilinx/cells_xtra.v
/usr/share/yosys/xilinx/drams.txt
/usr/share/yosys/xilinx/drams_map.v
/usr/share/yosys/xilinx/ff_map.v
/usr/share/yosys/xilinx/lut_map.v

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Fabrice Bellet, Mon May 9 14:21:55 2022